This paper presents an NMOS-only voltage reference with small process variations for ultra-low-power applications. All MOSFETs work in the subthreshold region and are biased by the leakage current of the NMOS transistor manufactured in Deep-N-Well (DNW). By fitting the variations of threshold voltage (VTH) from slow/fast corners to typical corners linearly, an optimum body selection (OBS) is proposed to reduce the impact of the process variations from VTH or ΔVTH with the aid of the body effect. The proposed design was fabricated in a 0.18-μm CMOS process, together with a baseline design without using the OBS. Based on the 25-chip measurement results, the output voltage variation of the proposed design is 0.0035 σ/μ, which is 61% smaller than that of the baseline design. Besides, for the proposed design with the OBS, the power consumption is 23pW (27∘C), while the die area is 0.003mm2. The temperature coefficient is 52ppm/∘C in a temperature range from 0∘C to 85∘C without trimming. The line sensitivity is 0.03%/V, and the power supply rejection ratio is 47dB at 100Hz.