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An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/H
Zhu Y.2; Chan C.-H.2; Martins R.P.2
2018-12-14
Conference Name2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018
Source Publication2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
Pages95-96
Conference Date5 November 2018 to 7 November 2018
Conference PlaceTainan
Abstract

This paper presents a 1GS/s 11 bit 4 × Time-Interleaved (TI) ADC employing the proposed Track-and-Hold (T/H) to enhance the sampling linearity and avoid timing skews. A dual auxiliary Source-Follower (SF) T/H provides signal double boosting to suppress the sampling distortion while maintaining good power efficiency. We present a dynamic SF-based switch boosting technique, providing a fast signal boost up and less signal attenuation to maximize the tracking duration and V of the sampling switch. A prototype in 65nm CMOS achieves SNDR of 55.8dB @Nyquist input and ERBW up to 2×Nyquist input with total 22mW power.

DOI10.1109/ASSCC.2018.8579311
URLView the original
Language英語English
Scopus ID2-s2.0-85060482053
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Citation statistics
Document TypeConference paper
CollectionUniversity of Macau
Affiliation1.Instituto Superior Técnico
2.Universidade de Macau
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Zhu Y.,Chan C.-H.,Martins R.P.. An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/H[C], 2018, 95-96.
APA Zhu Y.., Chan C.-H.., & Martins R.P. (2018). An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/H. 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings, 95-96.
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