Residential College | false |
Status | 已發表Published |
A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC | |
Jianyu Zhong1; Yan Zhu1; Chi-Hang Chan1; Sai-Wng Sin1; Seng-Pan U1,2,3; Rui Paulo Martins1,2 | |
2017-07-01 | |
Source Publication | IEEE Transactions on Circuits and Systems I: Regular Papers |
ISSN | 15498328 |
Volume | 64Issue:7Pages:1684-1695 |
Abstract | This paper presents a 12b 180 MS/s 0.068 mm $2\times$ time-interleaved pipelined-SAR analog-to-digital conver-ter (ADC) with gain and offset calibrations fully embedded on-chip. The proposed binary-search gain calibration (BSGC) technique corrects the inter-stage gain error caused by the open-loop residue amplifier. The BSGC, fully integrated into the second-stage SAR ADC, contributes to a compact area. We improve the noise performance by implementing a merged-residue-DAC operation in the first-stage ADC. Also, we propose a dual-phase bootstrap technique to improve the sampling linearity in the partial interleaving architecture. The measurement results of the ADC prototype in 65 nm CMOS demonstrate the effectiveness of the proposed calibration through the enhancement of the signal to noise-and-distortion ratio from 51.5 to 60.9 dB at a Nyquist input, leading to a FoM@Nyq of 36.7 fJ/conversion-step. |
Keyword | Analog-to-digital Converter (Adc) Low Power Successive Approximation Architecture Switched-capacitor Circuits |
DOI | 10.1109/TCSI.2017.2679748 |
URL | View the original |
Indexed By | SCIE |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:000404294900005 |
Scopus ID | 2-s2.0-85016398642 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING INSTITUTE OF MICROELECTRONICS |
Affiliation | 1.State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China 2.Synopsys Macau Ltd., Macao, China 3.Instituto Superior Técnico, Universidade de Lisboa, 1600-276 Lisboa, Portugal |
First Author Affilication | University of Macau |
Recommended Citation GB/T 7714 | Jianyu Zhong,Yan Zhu,Chi-Hang Chan,et al. A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2017, 64(7), 1684-1695. |
APA | Jianyu Zhong., Yan Zhu., Chi-Hang Chan., Sai-Wng Sin., Seng-Pan U., & Rui Paulo Martins (2017). A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(7), 1684-1695. |
MLA | Jianyu Zhong,et al."A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC".IEEE Transactions on Circuits and Systems I: Regular Papers 64.7(2017):1684-1695. |
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