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Status | 已發表Published |
A 2-μW 45-nV/√Hz Readout Front End with Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop | |
Jiangchao Wu1; Man-Kay Law2; Pui-In Mak1; Rui P. Martins1 | |
2016-04-01 | |
Source Publication | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS |
ISSN | 15497747 |
Volume | 63Issue:4Pages:351-355 |
Abstract | This brief presents an ultra-low-power low-noise chopped capacitively coupled instrumentation amplifier (CCIA) that is suitable for neural recording applications. An active high-pass filter is embedded in the ripple reduction loop (RRL) to suppress the residual noise and relax the capacitor size. Multiple chopping is employed to further reduce the residual output ripple due to the RRL offsets. A dc servo loop (DSL) using a 14-nA pseudofeedback amplifier is proposed to achieve a subhertz high-pass corner while using only a 15-pF on-chip capacitor. The complete CCIA is implemented in a standard 0.18-μm CMOS process. It occupies an area of 0.23 mm (including the DSL) and consumes 1.7 μA from a 1.25-V supply, achieving a noise efficiency factor of 2.9 that compares favorably with the state of the art. |
Keyword | Capacitively Coupled Instrumentation Amplifier (Ccia) Dc Servo Loop (Dsl) Multiple Chopping Neural Recording Front End Pseudofeedback Amplifier Ripple Reduction Loop (Rrl) |
DOI | 10.1109/TCSII.2015.2504944 |
URL | View the original |
Indexed By | SCIE |
Language | 英語English |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:000373137300007 |
Scopus ID | 2-s2.0-84963976995 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) Faculty of Science and Technology INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
Corresponding Author | Man-Kay Law |
Affiliation | 1.State Key Laboratory of Analog and MixedSignal VLSI and FST-ECE, University of Macau, Macao, China 2.State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China |
First Author Affilication | Faculty of Science and Technology |
Corresponding Author Affilication | University of Macau |
Recommended Citation GB/T 7714 | Jiangchao Wu,Man-Kay Law,Pui-In Mak,et al. A 2-μW 45-nV/√Hz Readout Front End with Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63(4), 351-355. |
APA | Jiangchao Wu., Man-Kay Law., Pui-In Mak., & Rui P. Martins (2016). A 2-μW 45-nV/√Hz Readout Front End with Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 63(4), 351-355. |
MLA | Jiangchao Wu,et al."A 2-μW 45-nV/√Hz Readout Front End with Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 63.4(2016):351-355. |
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