This brief presents a hybrid PLL by leveraging the advantages of analog and digital techniques in the frequency-control loop to achieve ultra-compact area and ultra-low power consumption simultaneously. Specifically, the hybrid loop consists of two paths: an integral path features a charge-sharing integrator realized by switched capacitors with high precision in digital discrete integration to improve the frequency resolution without deteriorating the output phase noise, and a proportional path directly switches the bias voltage of the VCO varactors to compensate the phase margin without costing extra power and area. Both paths are digitally controlled by a tiny power-efficient 1-bit bang-bang phase detector (BBPD). Prototyped in 28-nm CMOS, the 1.3-to-2.3-GHz PLL occupies a core area of 600 µm² and dissipates 380 µW at a 0.8-V supply, of which only 30 µW is due to the hybrid loop. At a 2.0-GHz output, the PLL exhibits a reference spur of −60.5 dBc and a jitter of 1.71 ps_rms, resulting in state-of-the-art FoMR of −239.5 dB, and FoMNRA of −271.7 dB.