This paper presents a 12-bit 110MS/s 4-stage pipelined SAR ADC integrated through a single low-gain op-amp. A ratio-based GEC (Gain Error Calibration) technique based on op-amp sharing is proposed to reduce the complexity of digital calibration circuit. Only one PN (Pseudo-random Number) signal is employed to perform the dither injection but calibrate multiple gain errors, and thus accelerates the convergence speed, gets rid of input signal reduction and minimizes the analog modification due to the background calibration. The effectiveness of the architecture is verified in 65-nm CMOS chips whose analog core area is 0.12 mm only. The ADC obtains an average SNDR of 63 dB and SFDR of 75.2 dB at 110MS/s consuming analog power of 11.5mW from a 1.2-V supply. Only 40 thousand points are needed to achieve desirable SNDR with the proposed calibration technique. © 2012 IEEE.