A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS

doi:10.1109/ESSCIRC.2012.6341364

UM > Faculty of Science and Technology > DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

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	A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS
	Guohe Yin 1,2; He-Gong Wei2 ; U–Fat Chio2 ; Sai-Weng Sin2 ; Seng-Pan U 2; Zhihua Wang 1; Rui Paulo Martins 2,3
	2012-12-14
Conference Name	European Solid-State Circuits Conference
Source Publication	2012 Proceedings of the ESSCIRC (ESSCIRC)
Pages	377-380
Conference Date	17-21 Sept. 2012
Conference Place	Bordeaux, France
Abstract	This paper presents a Successive Approximation Register Analog-to-Digital Converter (SAR ADC) design for sensor applications. An energy-saving switching technique is proposed to achieve ultra low power consumption. The measured Signal-to-Noise-and-Distortion Ratio (SNDR) of the ADC is 58.4 dB at 2 MS/s with an ultra-low power consumption of only 6.6 μW from a 0.8V supply, resulting in a Figure-Of-Merit (FOM) of 4.9 fJ/conversion-step. The prototype is fabricated in 65 nm CMOS technology with an area of 0.024 mm. © 2012 IEEE.
Keyword	Analgo-to-digital Converter Successive Approximation Register Ultra-low Power Sensor Applications
DOI	10.1109/ESSCIRC.2012.6341364
URL	View the original
Indexed By	其他
Language	英語English
Scopus ID	2-s2.0-84870836849
Fulltext Access	View Full-Text via DOI View Full-Text via Scopus
Citation statistics
Document Type	Conference paper
Collection	DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING Faculty of Science and Technology INSTITUTE OF MICROELECTRONICS
Affiliation	1.Institute of Microelectronics, Tsinghua University, Beijing, China 2.State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China 3.On leave from Instituto Superior Técnico/TU of Lisbon, Portugal
First Author Affilication	Faculty of Science and Technology
Recommended Citation GB/T 7714	Guohe Yin,He-Gong Wei,U–Fat Chio,et al. A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS[C], 2012, 377-380.
APA	Guohe Yin., He-Gong Wei., U–Fat Chio., Sai-Weng Sin., Seng-Pan U., Zhihua Wang., & Rui Paulo Martins (2012). A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS. 2012 Proceedings of the ESSCIRC (ESSCIRC), 377-380.

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