Excess Loop Delay (ELD) induced feedback DAC nonideality is a dominant factor causing error in the transfer function of CT ΣΔ modulators and eventually leading to instability. This paper will present a novel technique which aims to track the amount of excess loop delay, and compensate by using digital logic elements and an RC feedback network. A 2 order CT ΣΔ modulator with 1-bit DAC was built at transistor-level in 65nm CMOS to demonstrate the efficiency of the method. The Cadence simulation results show that, by using the proposed technique, the modulator can track the ELD up to 50% of the clock period duration and compensate it, leading to 69.2dB SNDR when compared with the ideal value of 70dB SNDR.