Aggressive CMOS technology scaling has been driving the design of analog-to-digital converters (ADCs) into new era in which many well-established conventional circuit techniques need to be largely modified to cater for the reduced supply headroom as well as the diminishing intrinsic gain of the transistors. However, the design of ADCs can surely benefits from the technology scaling by smart designs, due to the smaller transistors in nanometer CMOS, which is the key factor that the ADC can manipulate the signals with higher signal processing speed as well as reduced significantly the power consumption. This paper will present the design techniques, including the architectural improvements, power reduction and linearity improvement techniques for successful implementation of various examples of high-speed ADCs with high power efficiency in the state-of-the-art nanometer CMOS technology. © 2011 IEEE.