| Residential College | false |
| Status | 已發表Published |
| A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation | |
Zhu Y.1  ; Chan C.-H.1; Sin S.-W.1; Seng-Pan U.1; Martins R.P.1,2; Maloberti F.1,3
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| 2011-12-01 | |
| Conference Name | Asian Solid-State Circuits Conference (A-SSCC) |
| Source Publication | 2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011
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| Pages | 61-64 |
| Conference Date | NOV 14-16, 2011 |
| Conference Place | Jeju, SOUTH KOREA |
| Abstract | A Time-Interleaved (TI) pipelined-SAR ADC with on-chip offset cancellation technique is presented. The design reuses the SAR ADC to perform offset cancellation, which significantly saves calibration area, power and time. A 6 bit capacitive DAC is built as a flip-around MDAC for low inter-stage gain implementation. The capacitive attenuation solutions in both 1 and 2 DACs minimize the power dissipation and optimize conversion speed. Measurements of a 65nm CMOS prototype operating at 160MS/s and 1.1V supply show 2.72mW total power consumption. The SNDR is 55.4dB and the FoM as low as 35fJ/conv.-step. © 2011 IEEE. |
| DOI | 10.1109/ASSCC.2011.6123604 |
| URL | View the original |
| Indexed By | SCIE ; CPCI-S |
| Language | 英語English |
| WOS Research Area | Engineering |
| WOS Subject | Engineering, Electrical & Electronic |
| WOS ID | WOS:000310888200007 |
| Scopus ID | 2-s2.0-84863030908 |
| Fulltext Access | |
| Citation statistics | |
| Document Type | Conference paper |
| Collection | INSTITUTE OF MICROELECTRONICS Faculty of Science and Technology DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
| Affiliation | 1.State-Key Laboratory of Analog and Mixed Signal VLSI, Faculty of Science and Technology, University of Macau, Macao, China 2.On leave from Instituto Superior Técnico/TU of Lisbon, Portugal 3.University of Pavia, Italy |
| First Author Affilication | Faculty of Science and Technology |
| Recommended Citation GB/T 7714 | Zhu Y.,Chan C.-H.,Sin S.-W.,et al. A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation[C], 2011, 61-64. |
| APA | Zhu Y.., Chan C.-H.., Sin S.-W.., Seng-Pan U.., Martins R.P.., & Maloberti F. (2011). A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation. 2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011, 61-64. |
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