An 11b 60MS/s 2-channel two-step SAR ADC in 65nm CMOS is presented. The scheme shares the op-amp between channels for the residual generation and takes advantage of time interleaving for reusing the input S&H of the first stage. A reduction of the gain in the residual generator and subthreshold operation enables the use of a power-effective, single-stage op-amp with 69dB-gain. The ADC achieves peak SNDR of 57.6dB while consuming 2.1mW from 1-V analog and 0.85-V digital supply, resulting in an FoM of 57fJ/step. ©2010 IEEE.