This paper proposes the design of a binary search ADC that uses two different techniques, namely, distributed-residue and folding. These can prevent signal dependent offset and reduce the switching network complexity. A 5-bit binary-search ADC applying such proposed techniques has been developed in 65 nm CMOS. It consumes 540 μW under 1V supply voltage at the operating frequency of 600 MS/s. The simulation results demonstrate that the design achieves a SNDR of 30.8 dB at Nyquist input frequency with a figure of merit (FOM) of 32 fJ/conversion-step. © 2010 IEEE.