This paper presents an improved front-end digitizer for pipeline/two-step ADC. It achieves a high linearity by replacing the front-end stage's sub-ADC from the flash type that involves synchronous operation of several comparators, to the one that uses successive approximation (SA). This shift not only frees the ADC from an extra front-end sample-and-hold circuit, but also guarantees an inherent monotonicity because of no comparator mismatch (since the SA-ADC involves just one comparator in recursive operation). Two examples of a 100-MHz 3.5-bit/stage pipeline ADC and an 11-bit 30-MHz two-step ADC, validate the feasibility of such a digitizer. © 2007 IEEE.