This paper presents an incremental A/D converter with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise coupling path is then enabled in the exponential phase thus boosting the SQNR exponentially with a few number of clock cycles. The uniform-exponential weight function allows data weighted averaging (DWA) to work well suppressing the DAC mismatch error. Fabricated in 65nm CMOS under 1.2V supply, the ADC achieves an SNDR/DR of 100.8dB/101.8dB with 20kHzBW, 550μW 0.134mm, resulting in FoMw and FoMs of 153fJ/176.4dB (SNDR), respectively.