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A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure
Song Y.3; Zhu Y.3; Chan C.-H.3; Geng L.1; Martins R.P.3
2018-10-22
Conference Name2018 IEEE Symposium on VLSI Circuits
Source PublicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2018-June
Pages203-204
Conference Date18-22 June 2018
Conference PlaceHonolulu, HI, USA
Abstract

This paper presents a wide-band and energy-efficient 0-1 MASH ΣΔ ADC which is realized based on the pipelined-SAR structure. Composed by a 6b SAR ADC in the 1-stage and a 5b SAR ADC in the 2-stage, with alternate loading capacitors (ALC) reused for error feedback, it realizes an ideal 1-order noise shaping while simultaneously maintaining a high-speed pipeline operation. Fabricated in 65nm CMOS, the prototype consumes 4.5mW from a 1.2V supply with 77dB SNDR over 12.5MHz bandwidth, leading to a 171.5dB Schreier FoM.

KeywordΣδ Adc Pipelined-sar Adc
DOI10.1109/VLSIC.2018.8502382
URLView the original
Language英語English
WOS IDWOS:000853983300080
The Source to ArticlePB_Publication
Scopus ID2-s2.0-85056813465
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Citation statistics
Document TypeConference paper
CollectionINSTITUTE OF MICROELECTRONICS
Affiliation1.Xi'an Jiaotong University
2.Instituto Superior Técnico
3.Universidade de Macau
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Song Y.,Zhu Y.,Chan C.-H.,et al. A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure[C], 2018, 203-204.
APA Song Y.., Zhu Y.., Chan C.-H.., Geng L.., & Martins R.P. (2018). A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure. IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 2018-June, 203-204.
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