A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector

doi:10.1109/NorCAS57515.2022.9934542

UM > THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU)

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	A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector
	Ge, Xinyi 1; Chen, Yong1 ; Wang, Lin 1; Qi, Nan 2; Mak, Pui In 1; Martins, Rui P.1,3
	2022-11-08
Conference Name	8th IEEE Nordic Circuits and Systems Conference (NorCAS)
Source Publication	2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings
Conference Date	OCT 25-26, 2022
Conference Place	Oslo, NORWAY
Publisher	IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA
Abstract	This paper reports a 28-Gb/s bang-bang clock and data recovery (CDR) circuit based on the proposed phase detector (BBPD) including four sample flip-flops, two combined XORs, and a voltage-to-current converter. We employ a charge-steering technique to minimize power consumption, inserting one additional branch with a combined XOR into the proposed BBPD, to detect all code types. The CDR prototype pulls-off a 523.7-fs jitter performance with 13.8-mW power consumption.
Keyword	Bang-bang Phase Detector (Bbpd) Charge Steering Clock And Data Recovery (Cdr) Cmos Half Rate Non- Return-to-zero (Nrz) Quadrature Voltage-controlled Oscillator (Qvco) Return-to-zero (Rz) Rz-to-nrz Converter
DOI	10.1109/NorCAS57515.2022.9934542
URL	View the original
Indexed By	CPCI-S
Language	英語English
WOS Research Area	Computer Science ; Engineering
WOS Subject	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS ID	WOS:000889469600015
Scopus ID	2-s2.0-85142447370
Fulltext Access	View Full-Text via DOI View Full-Text via Web of Science View Full-Text via Scopus
Citation statistics
Document Type	Conference paper
Collection	THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) INSTITUTE OF MICROELECTRONICS
Corresponding Author	Chen, Yong
Affiliation	1.University of Macau, State Key Laboratory of Analog and Mixed-Signal Vlsi and IME/FST-ECE, Macao 2.Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China 3.Instituto Superior Técnico, Universidade de Lisboa, Portugal
First Author Affilication	Faculty of Science and Technology
Corresponding Author Affilication	Faculty of Science and Technology
Recommended Citation GB/T 7714	Ge, Xinyi,Chen, Yong,Wang, Lin,et al. A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector[C]:IEEE, 345 E 47TH ST, NEW YORK, NY 10017 USA, 2022.
APA	Ge, Xinyi., Chen, Yong., Wang, Lin., Qi, Nan., Mak, Pui In., & Martins, Rui P. (2022). A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector. 2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings.

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