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| Status | 已發表Published |
| A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur | |
Huang, Yunbo1; Chen, Yong1  ; Zhao, Bo2; Mak, Pui In1; Martins, Rui P.1,3
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| 2023-04-01 | |
| Source Publication | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
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| ISSN | 1549-8328 |
| Volume | 70Issue:4Pages:1463-1475 |
| Abstract | This paper reports an active-buffer-free type-I sampling phase-locked loop (S-PLL). We innovate a fully-passive sampling phase detector with passive-gain multiplication after the sampler, resulting in a stably-boosted PD gain and better linearity. Together with a transformer-based rich-harmonic shaping voltage-controlled oscillator, the proposed S-PLL at 3.78 GHz exhibits an integrated jitter of 39.6 fsRMS (1 kHz to 100 MHz), and the jitter-power figure-of-merit scores -260.2 dB. The reference (REF) spur is -70.96 dBc due to the embedded REF-feedthrough suppression technique. |
| Keyword | Cmos Type-i Sampling Phase-locked Loop (S-pll) Voltage-controlled Oscillator (Vco) Reference (Ref) Feedthrough Suppression Figure-of-merit (Fom) Phase-detection Gain (Kpd) Sampling Phase Detector (S-pd) |
| DOI | 10.1109/TCSI.2023.3236309 |
| URL | View the original |
| Indexed By | SCIE |
| Language | 英語English |
| WOS Research Area | Engineering |
| WOS Subject | Engineering, Electrical & Electronic |
| WOS ID | WOS:000920575400001 |
| Publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 |
| Scopus ID | 2-s2.0-85147285374 |
| Fulltext Access | |
| Citation statistics | |
| Document Type | Journal article |
| Collection | Faculty of Science and Technology THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) CENTRE FOR ENGINEERING RESEARCH AND TESTING DEPARTMENT OF COMPUTER AND INFORMATION SCIENCE |
| Corresponding Author | Chen, Yong |
| Affiliation | 1.State-Key Laboratory of Analog and Mixed Signal VLSI and IME/ECE-FST, University of Macau, Macau 999078, China 2.Zhejiang University, Institute of Vlsi Design, Hangzhou, 310027, China 3.Universidade de Lisboa, Instituto Superior Técnico, Lisboa, 1049-001, Portugal |
| First Author Affilication | Faculty of Science and Technology |
| Corresponding Author Affilication | Faculty of Science and Technology |
| Recommended Citation GB/T 7714 | Huang, Yunbo,Chen, Yong,Zhao, Bo,et al. A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2023, 70(4), 1463-1475. |
| APA | Huang, Yunbo., Chen, Yong., Zhao, Bo., Mak, Pui In., & Martins, Rui P. (2023). A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 70(4), 1463-1475. |
| MLA | Huang, Yunbo,et al."A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary-Secondary S-PD Measuring 39.6-fsRMSJitter, -260.2-dB FOM, and -70.96-dBc Reference Spur".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 70.4(2023):1463-1475. |
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