Residential College | false |
Status | 已發表Published |
Universal Stability Criterion for Type-I Sampling Phase-Locked Loops | |
Huang, Yunbo1; Chen, Yong1; Mak, Pui In1; Martins, Rui P.1,2 | |
2023-04-01 | |
Source Publication | IEEE Transactions on Circuits and Systems II: Express Briefs |
ISSN | 1549-7747 |
Volume | 70Issue:4Pages:1351-1355 |
Abstract | This brief reports a universal stability criterion for the type-I sampling phase-locked loop (S-PLL). The linear-time- variant model predicts with precision a maximum phase margin that decreases linearly with the increasing loop bandwidth (BW), leading to a maximum achievable loop BW that is half of the reference frequency. We verified the derived theory through extensive simulations and will present a guide that is useful in the design and optimization of different S-PLL schemes. |
Keyword | Given Phase Margin (Pm) Linear Time-variant (Ltv) Mode Sampling Phase-locked Loop (S-pll) Sub-sampling Pll (ss-Pll) Type-i Voltage-controlled Oscillator (Vco) |
DOI | 10.1109/TCSII.2022.3231536 |
URL | View the original |
Indexed By | SCIE |
Language | 英語English |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:000965682400001 |
Publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 |
Scopus ID | 2-s2.0-85146228212 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) Faculty of Science and Technology INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
Corresponding Author | Chen, Yong |
Affiliation | 1.University of Macau, State-Key Laboratory of Analog and Mixed-Signal Vlsi and IME/ECE-FST, Macao 2.Instituto Superior Técnico, Universidade de Lisboa, Lisboa, 1049-001, Portugal |
First Author Affilication | Faculty of Science and Technology |
Corresponding Author Affilication | Faculty of Science and Technology |
Recommended Citation GB/T 7714 | Huang, Yunbo,Chen, Yong,Mak, Pui In,et al. Universal Stability Criterion for Type-I Sampling Phase-Locked Loops[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(4), 1351-1355. |
APA | Huang, Yunbo., Chen, Yong., Mak, Pui In., & Martins, Rui P. (2023). Universal Stability Criterion for Type-I Sampling Phase-Locked Loops. IEEE Transactions on Circuits and Systems II: Express Briefs, 70(4), 1351-1355. |
MLA | Huang, Yunbo,et al."Universal Stability Criterion for Type-I Sampling Phase-Locked Loops".IEEE Transactions on Circuits and Systems II: Express Briefs 70.4(2023):1351-1355. |
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