eal-time speech recognizers and translators rely on an always-on voice activity detector (VAD) to enable and disable the main system for effective power savings. A feature extractor and a memoryless classifier build the basic structure of the recent VADs, as depicted in Fig. 13.2.1 (upper-left). The feature extractor [1], [2] using Mel-frequency cepstral coefficients (MFCCs) regrettably occupies a substantial area and incurs a long latency for an extraction window of 16 to 25ms to cover a frequency down to sim 100Hz. For example, the required filter bank in [1] consumes 1muW r with a 25ms extraction window, leading to a 30ms latency. The mixer-based analog filter in [2] succeeds in squeezing the feature extractor's power to 60nW by using a time-interleaved fashion, but the latency prolongs to 512ms. The time-domain convolutional neural network (TD-CNN) in [3] exploiting passive switched-capacitor computation saves both the power and area of the feature extractor. Still, the area of the analog memory, and the signal leakage within the extraction window (10ms), are large. Its large threshold in the sensitivity threshold control also incurs in a latency of 50ms to sustain the VAD hit rate. Finally, all [1]-[3] require area-and-power-hungry on-chip memory to store the network parameters, preloading them to the volatile memory for every power-on increases the system complexity substantially.