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Status | 已發表Published |
A High-Current Scalable Parallel LDO Scheme With Analog-Digital Merged Control for Small Current-Sharing Mismatch | |
Mao,Xiangyu1; Lu,Yan1; Wang,Chuang1; Martins,Rui P.2 | |
2023-07-18 | |
Source Publication | IEEE Transactions on Circuits and Systems I: Regular Papers |
ISSN | 1549-8328 |
Volume | 70Issue:10Pages:3857 - 3866 |
Abstract | Parallel connected low-dropout regulators (LDOs) are commonly used to share the large load current in communication baseband systems. This paper presents a PCB-friendly, reconfigurable master-slave parallel LDO scheme with analog regulation and digital distribution, to deliver Ampere-level load current with small current mismatches. The proposed LDO adopts a series analog-digital merged control, where the first loop is a high-gain analog error amplifier for high-accuracy regulation, and the second loop utilizes a 6-bit successive approximation register (SAR) analog-to-digital converter (ADC) for the tradeoffs between resolution, energy-efficiency, and fast response. Each LDO can be configured into the master or slave mode. When multiple LDOs are connected in parallel, the master LDO also controls the digital power cells in the slave LDOs. By employing an auxiliary constant current control, the power cells in each LDOs work as a constant current source array. The same control code naturally enables the output current balancing among each LDOs. Fabricated in 65-nm CMOS, the proposed LDO obtains an excellent load regulation of $<$ 1.5mV/A across the full load range of 0-1A, with 99.9% peak current efficiency. For four parallel LDOs with each delivering 1-A load current, the measured current-sharing mismatch is only $<$ 0.76% with no additional external components. |
Keyword | Low-dropout Regulator (Ldo) Hybrid Control Master-slave Parallel Current-sharing Dual-loop Control |
DOI | 10.1109/TCSI.2023.3293133 |
URL | View the original |
Indexed By | SCIE |
Language | 英語English |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:001040806100001 |
Scopus ID | 2-s2.0-85165291607 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
Corresponding Author | Lu,Yan |
Affiliation | 1.Institute of Microelectronics, State Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China 2.FST-DECE, University of Macau, Macau, China |
First Author Affilication | University of Macau |
Corresponding Author Affilication | University of Macau |
Recommended Citation GB/T 7714 | Mao,Xiangyu,Lu,Yan,Wang,Chuang,et al. A High-Current Scalable Parallel LDO Scheme With Analog-Digital Merged Control for Small Current-Sharing Mismatch[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(10), 3857 - 3866. |
APA | Mao,Xiangyu., Lu,Yan., Wang,Chuang., & Martins,Rui P. (2023). A High-Current Scalable Parallel LDO Scheme With Analog-Digital Merged Control for Small Current-Sharing Mismatch. IEEE Transactions on Circuits and Systems I: Regular Papers, 70(10), 3857 - 3866. |
MLA | Mao,Xiangyu,et al."A High-Current Scalable Parallel LDO Scheme With Analog-Digital Merged Control for Small Current-Sharing Mismatch".IEEE Transactions on Circuits and Systems I: Regular Papers 70.10(2023):3857 - 3866. |
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