Neuromorphic devices capable of training spiking neural networks (SNNs) are not easy to develop due to two main factors: lack of efficient supervised learning algorithms, and high computational requirements that ultimately lead to higher power consumption and higher cost. In this article, we present an FPGA-based neuromorphic system capable of training SNNs efficiently. The Tempotron learning rule along with population coding is adopted for SNN learning to achieve a high level of classification accuracy. To blend cost efficiency with high throughput, integration of both integrate-and-fire (IF) and leaky integrate-and-fire (LIF) neurons is proposed. Moreover, the post-synaptic potential (PSP) kernel function for the LIF neuron is modeled using slopes. This novel solution obviates the need for multipliers and memory accesses for kernel computations. Experimental results show that a speedup of about 15 × can be obtained on a general-purpose Von-Neumann device if the proposed scheme is adopted. Moreover, the proposed neuromorphic design is fully parallelized and can achieve a maximum throughput of about 2460 × 10 4-input samples per second, while consuming only 13.6 slice registers per synapse and 89.5 look-up tables (LuTs) per synapse on Virtex 6 FPGA. The system can classify an input sample in about 4.88 ns.