Almost every electronic system demands a clock signal with high spectral purity. Wireless or wireline systems typically rely on two approaches to enhance the data rate: (1) employing a denser modulation scheme and (2) increasing the operating frequency to secure a large bandwidth. Both approaches impose stringent requirements on the phase noise or jitter of the clock signal. Also, the clock generator needs to be power-efficient in order to improve the battery life of a mobile terminal or save energy dissipation in the data center. This chapter elaborates VCO (voltage-controlled oscillator) and PLL (phase-locked loop) designs, two critical components of a clock generator. The first and third designs demonstrate how the harmonic shaping techniques help to improve the phase noise of the RF and mm-wave VCOs. The second presents an inductive mode-switching technique that can increase the frequency tuning range of the mm-wave VCO without compromising the phase noise. The fourth work is a 25.5–29.9 GHz subsampling (SS) PLL utilizing a master-slave isolated subsampling phase detector to simultaneously obtain low jitter and low reference spur. We verified all four designs with silicon results in 65 nm CMOS (complementary metal-oxide semiconductor).