This article presents a power-delay-optimized monotonic-specific successive approximation register (SAR) ADC. The SAR feedback loop, comprising the proposed unbalanced N/P-MOS sizing technique, simultaneously reduces the SAR logic delay and the power to overcome the SAR ADC’s speed bottleneck. Benefiting from this technique, the sampling rate of the prototype 10b single channel 1b/cycle SAR ADC reaches 600 and 700 MS/s at 0.9 and 0.95 V supply voltage, while consuming 1.49 and 2.02 mW in 28 nm CMOS, respectively. Moreover, the 10b ADC achieves the SNDR of 56.39 and 56.42-dB at a Nyquist rate input frequency of 600 and 700 MS/s, leading to a Walden FoM of 4.6 and 5.3 fJ/conversion-step, respectively.