| Status | 已發表Published |
| Title | Advanced Techniques in Analog to Digital Converters |
| Author | Xing, D.; U, S.P.; Zhu, Y. ; Sin, S. W.
|
| Date Issued | 2018-12-01 |
| Keyword | Analog to Digital Converters |
| Abstract | The high-speed power efficient analog-to-digital converters (ADCs) are in high demand by most communication systems. With the CMOS technology scaling down, achieving high linearity, high sampling rate, and high dynamic range, with low supply voltages and low power dissipation is a major challenge in designing analog circuits. The digital nature of Successive-Approximation-Register (SAR) ADC makes it a good candidate for energy-efficient and scalable design. However, its speed and resolution are limited due to capacitor matching, comparator noise and the binary search algorithm nature. This thesis investigates the limitations and design challenges of high-speed low-power SAR-type ADC, which includes common mode variation induced by some popular switching technique as well as the optimization of ADC architecture. The designs of high-performance SAR-type ADC integrated with novel circuit techniques to improve the conversion linearity, enhance the speed and relax the reference interference are presented. The first design presents a 7-bit 700-MS/s 4-way time-interleaved (TI) SAR ADC. A partial Vcm-based switching method is proposed that requires less digital overhead from the SAR controller and achieves better conversion accuracy. When compared with switchback switching, the proposed method can further reduce the common mode variation by 50%. Also, the impacts of such reduction on the comparator offset, noise and input parasitic are theoretically analyzed and verified by simulation. The prototype fabricated in 65 nm CMOS technology occupies an active area of 0.025 mm2. Measurement results at the 700 MS/s sampling rate show that the ADC achieves signal-to-noise-and-distortion ratio (SNDR) of 40 dB @ Nyquist input and consumes 2.72 mW from a 1.2 V supply, which results in a Walden Figure of Merit (FoM) of 48 fJ/conv.-step. In the second design, the design methodologies for high-speed SAR ADCs are discussed. A comparison of various architectures and the study of benefits and limits identifies the best solution for high-speed and medium resolution. It is an interleaving architecture with the channel implemented by a fast coarse SAR quantizer and 2-way TI fine SAR ADCs. We propose a float-then-write (FTW) code transfer technique for optimizing the transfer sequence and reducing the reference interference. Furthermore, we also study and compare the output impedance of the reference generation as well as the reference interference for the optimized code transfer scheme and the conventional bit-by-bit in both single channel and TI scenarios. Also, the mismatches in TI channels and two sub-ADCs are discussed. A 10-bit test vehicle fabricated in 65-nm CMOS confirms experimentally the proposed methods operating with 1.2 V supply at 700 MS/s. The circuit occupies an active area of 0.084 mm2 and achieves an SNDR at Nyquist of 53.3 dB, with a power consumption of 9.5 mW. The Walden FoM is 36 fJ/conversion-step. |
| Language | 英語English |
| PUB ID | 48567 |
| Document Type | Thesis |
| Collection | INSTITUTE OF MICROELECTRONICS |
| Recommended Citation GB/T 7714 | Xing, D.,U, S.P.,Zhu, Y.,et al. Advanced Techniques in Analog to Digital Converters[D], 2018. |
| Files in This Item: | There are no files associated with this item. | |||||
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