This brief presents a compact and power-efficient full ring-oscillator (RO)-based cascaded fractional-N PLL. The proposed cascaded PLL consists of a RO-based DLL and type-II PLL as the first and second stages, respectively. The first stage serves as a frequency multiplier that increases the operating frequency of the delta-sigma modulator (DSM) in the second stage, thereby suppressing its quantization noise. A burst-mode sampling (BMS) scheme is introduced to improve the phase noise (PN) of the frequency multiplier and achieves a PN multiplication factor removal. Implemented in a 28nm CMOS technology, the PLL prototype occupies a 0.016 mm2 active area, achieving a 686 fs integrated rms jitter from 10KHz to 40MHz at a 4 GHz output frequency; while consuming 10.21mW with −233.6 dB FoMjitter. The measured fractional and reference spurs are −59.8 dBc and −54.5 dBc, respectively.