A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM

doi:10.1109/ESSCIRC59616.2023.10268691

UM > THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU)

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	A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM
	Shen, Xinyu 1,2; Zhang, Zhao 1,2; Li, Guike 1,2; Chen, Yong3 ; Qi, Nan 1,2; Liu, Jian 1,2; Wu, Nanjian 1,2; Liu, Liyuan 1,2
	2023-10
Conference Name	ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)
Source Publication	Proceedings of the European Solid-State Circuits Conference
Volume	2023-September
Pages	257-260
Conference Date	11-14 September 2023
Conference Place	Lisbon, Portugal
Country	Portugal
Publisher	IEEE
Abstract	This paper reports a fractional-N ring sampling phase-locked loop (FN-RSPLL). With the aid of our developed adaptively-biased phase-detector-merged digital-to-time converter, wideband loop bandwidth (LBW) tracking is achieved to keep the LBW almost constant within an ultrawide frequency tuning range (FTR) regardless of the supply voltage (VDD) variation. Thus, this enables robust operating at the over-10-GHz frequency with wide FTR and large LBW for jitter suppression. Realized in a 40-nm CMOS, our FN-RSPLL measures the FTR from 4 to 12.1 GHz and scores 261.9-fs RMS jitter and 1.27-mW/GHz power efficiency corresponding to 240.6-dB FoM. The integrated phase noise and LBW over the FTR are -37.6 ± 0.9 d B c and 34.4 ± 1.29 M H z, respectively. The jitter varies by 18.8 fSRMS (7.4%) covering a 0.95-1.1-V VDD.
Keyword	Cmos. Fractional-n(Fn) Loop Bandwidth Tracking Ring Sampling Phase-locked Loop (Rspll) Wideband
DOI	10.1109/ESSCIRC59616.2023.10268691
URL	View the original
Indexed By	CPCI-S
Language	英語English
WOS Research Area	Engineering ; Physics
WOS Subject	Engineering, Electrical & Electronic ; Physics, Applied
WOS ID	WOS:001088613100065
Scopus ID	2-s2.0-85175263705
Fulltext Access	View Full-Text via DOI View Full-Text via Web of Science View Full-Text via Scopus
Citation statistics
Document Type	Conference paper
Collection	THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) INSTITUTE OF MICROELECTRONICS
Corresponding Author	Zhang, Zhao
Affiliation	1.Institute of Semiconductors, Chinese Academy of Sciences, State Key Laboratory of Superlattices and Microstructures, Beijing, China 2.University of Chinese Academy of Sciences, Beijing, China 3.University of Macau, Macao
Recommended Citation GB/T 7714	Shen, Xinyu,Zhang, Zhao,Li, Guike,et al. A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM[C]:IEEE, 2023, 257-260.
APA	Shen, Xinyu., Zhang, Zhao., Li, Guike., Chen, Yong., Qi, Nan., Liu, Jian., Wu, Nanjian., & Liu, Liyuan (2023). A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM. Proceedings of the European Solid-State Circuits Conference, 2023-September, 257-260.

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