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A 10.5 W, 93% Efficient Dual-Path Hybrid (DPH)-Based DC-DC Converter Incorporating a Continuous-Current-Input Switched-Capacitor Stage and Enhanced IL Reduction for 12 V/24 V Inputs | |
Ma, Qiaobo2,3; Zhang, Xiongjie2,3; Zhao, Anyang2; Li, Huihua2,3; Jiang, Yang2,3; Law, Man Kay2,3; Takamiya, Makoto1; Martins, Rui P.2,3,4; Mak, Pui In2,3 | |
2023-10-12 | |
Source Publication | IEEE Transactions on Circuits and Systems I: Regular Papers |
ISSN | 1549-8328 |
Volume | 70Issue:12Pages:5482-5495 |
Abstract | This work proposes a high-step-down switched-capacitor (SC) hybrid DC-DC converter that effectively addresses the conduction loss in the inductor and power switches. Specifically, an architecture combining a dual-path hybrid (DPH) converter at the input, and a continuous-current-input SC (CISC) stage at the output, achieves superior performance in reducing the inductor DC current (I) compared to the existing single-inductor two-flying-capacitor (1L - 2C) converters. Also, the converter exploits low-voltage (LV) switches to handle a substantial portion of the current, diminishing the reliance on the inductor or high-voltage (HV) switches. Consequently, this approach enhances the efficiency and on-chip power/current density. The converter, implemented in 180-nm BCD, integrates monolithic power switches, drivers, and control circuitry. It is capable of regulating an output voltage within the range of 1.2 to 3.5 V, accommodating a 12 V/24 V-input. The peak efficiency is 93% and the on-chip current density is 0.638A/mm2. The load current delivery is up to 3 A, even using a compact inductor with a DC resistance (DCR) of 200 m Ω. |
Keyword | Current Density Dcr Loss Dual-path Hybrid Topology Inductor Current Reduction Switched-capacitor |
DOI | 10.1109/TCSI.2023.3320745 |
URL | View the original |
Indexed By | SCIE |
Language | 英語English |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:001085278900001 |
Publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC445 HOES LANE, PISCATAWAY, NJ 08855-4141 |
Scopus ID | 2-s2.0-85174800810 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | INSTITUTE OF MICROELECTRONICS Faculty of Science and Technology THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
Corresponding Author | Jiang, Yang |
Affiliation | 1.The University of Tokyo, Institute of Industrial Science, Tokyo, 153-8505, Japan 2.University of Macau, State Key Laboratory of Analog and Mixed-Signal Vlsi, Ime, Macau, Macao 3.University of Macau, Department of Ece, Fst, Macau, Macao 4.Universidade de Lisboa, On Leave from Instituto Superior Técnico, Lisbon, 1649-004, Portugal |
First Author Affilication | University of Macau; Faculty of Science and Technology |
Corresponding Author Affilication | University of Macau; Faculty of Science and Technology |
Recommended Citation GB/T 7714 | Ma, Qiaobo,Zhang, Xiongjie,Zhao, Anyang,et al. A 10.5 W, 93% Efficient Dual-Path Hybrid (DPH)-Based DC-DC Converter Incorporating a Continuous-Current-Input Switched-Capacitor Stage and Enhanced IL Reduction for 12 V/24 V Inputs[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 5482-5495. |
APA | Ma, Qiaobo., Zhang, Xiongjie., Zhao, Anyang., Li, Huihua., Jiang, Yang., Law, Man Kay., Takamiya, Makoto., Martins, Rui P.., & Mak, Pui In (2023). A 10.5 W, 93% Efficient Dual-Path Hybrid (DPH)-Based DC-DC Converter Incorporating a Continuous-Current-Input Switched-Capacitor Stage and Enhanced IL Reduction for 12 V/24 V Inputs. IEEE Transactions on Circuits and Systems I: Regular Papers, 70(12), 5482-5495. |
MLA | Ma, Qiaobo,et al."A 10.5 W, 93% Efficient Dual-Path Hybrid (DPH)-Based DC-DC Converter Incorporating a Continuous-Current-Input Switched-Capacitor Stage and Enhanced IL Reduction for 12 V/24 V Inputs".IEEE Transactions on Circuits and Systems I: Regular Papers 70.12(2023):5482-5495. |
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