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A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA | |
Tan, Gaofeng1; Qin, Xinyu1; Liu, Yan1; Guo, Mingqiang2; Sin, Sai Weng2; Wang, Guoxing1; Lian, Yong3; Qi, Liang1 | |
2023-12-01 | |
Source Publication | IEEE Transactions on Circuits and Systems I: Regular Papers |
ISSN | 1549-8328 |
Volume | 70Issue:12Pages:4781-4792 |
Abstract | This paper presents a continuous-time (CT) 0-4 dual-stage Multi-stAge Noise-sHaping (MASH) Delta-Sigma Modulator (DSM), exhibiting +5dBFS maximum stable amplitude (MSA). In the context of 0-4 MASH topology, the 4-bit CT DSM employed as the second stage only processes 4-bit quantization noise (QN) of the front-end. Though the input signal exceeds the full scale (FS), the second stage still stays stable as long as the signal leakage does not overload it. Such feature guarantees the improved stability over a wider signal input range. In addition, to address the well-known QN leakage issue of MASH topology, we propose to combine the feedforward topology with proportional-integral-based excess loop delay compensation. It ensures high robustness of the proposed 0-4 MASH DSM without requiring any calibration. Additionally, we present an analysis of the anti-aliasing filtering (AAF) for the 0-X MASH DSM. It is found that the overall AAF of the 0-X MASH DSM is contributed from the second stage. Sampled at 400MHz, the 65nm CMOS experimental prototype measures signal-to-noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 76.7dB/87.3dB over a 10MHz bandwidth with 15.1mW power consumption. Moreover, with achieving +5dBFS MSA, the dynamic range (DR) is extended to be as high as 85dB, resulting in a state-of-the-art Scherier Figure of Merit (FoM) of 173.2dB based on DR. |
Keyword | 0-x Mash Analog-to-digital Converter (Adc) Anti-aliasing Filtering Continuous Time (Ct) Maximum Stable Amplitude (Msa) Multi-stage Noise Shaping (Mash) |
DOI | 10.1109/TCSI.2023.3299931 |
URL | View the original |
Indexed By | SCIE |
Language | 英語English |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:001147346200001 |
Publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC445 HOES LANE, PISCATAWAY, NJ 08855-4141 |
Scopus ID | 2-s2.0-85168292588 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) Faculty of Science and Technology DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
Corresponding Author | Qi, Liang |
Affiliation | 1.Shanghai Jiao Tong University, Department of Micro-Nano Electronics, Shanghai, 200240, China 2.State-Key Laboratory of Analog and Mixed-Signal Vlsi, University of Macau, Macau, Macao 3.York University, Department of Electrical Engineering and Computer Science, Toronto, M3J 1P3, Canada |
Recommended Citation GB/T 7714 | Tan, Gaofeng,Qin, Xinyu,Liu, Yan,et al. A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12), 4781-4792. |
APA | Tan, Gaofeng., Qin, Xinyu., Liu, Yan., Guo, Mingqiang., Sin, Sai Weng., Wang, Guoxing., Lian, Yong., & Qi, Liang (2023). A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA. IEEE Transactions on Circuits and Systems I: Regular Papers, 70(12), 4781-4792. |
MLA | Tan, Gaofeng,et al."A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA".IEEE Transactions on Circuits and Systems I: Regular Papers 70.12(2023):4781-4792. |
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