This article presents an excess loop delay compensation (ELDC) free 20 MHz bandwidth (BW) fourth-order continuous-time sigma-delta modulator (CT SDM) facilitated by a noise-shaping continuous-time successive-approximation register (NS CT-SAR) ADC. The modulator comprises a second-order single amplifier biquad (SAB) loop filter (LF) and a second-order NS CT-SAR with a passive integrator. The NS CT-SAR provides a stable second-order NS with a dedicated reset operation to ensure a robust input biasing for its CT interface. With ping-pong operation in the passive integrator, the delay of the 6b CT quantizer (QTZ) with 1b redundancy reduces to only one SA cycle, thus enabling the ELDC-free design. An ac-coupled negative-R is introduced to support the SAB integrator, which achieves low power and maintains a stable performance at band-edge input. The prototype is fabricated in 28-nm CMOS technology, occupying an active area of 0.037 mm2. It achieves 75.5-dB SNDR with 20 MHz BW at 750 MHz sampling frequency while consuming 2.78 mW from 1.5 to 1 V supply voltage. The proposed SDM yields a Walden figure-of-merit (FoMw) of 14.3 fJ/conversion step and a Schreier FOM (FoMS) of 174.1 dB, which are competitive among single loop architectures with similar sampling frequency and BW, while this design is ELDC-free.