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Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique | |
Yi Mao1; Gengzhen Qi1; MAK PUI IN2 | |
2014-04-16 | |
Source Publication | IEEE Open Journal of Circuits and Systems |
ISSN | 2644-1225 |
Volume | 5Pages:92-101 |
Abstract | This paper reports a wideband blocker-tolerant receiver (RX) that covers a 0.5-to-2 GHz radio frequency (RF) range. By combining the gain-boosted (GB) mixer-first low-noise amplifier (LNA) network with a bottom-plate switched-capacitor (SC) N-path filter, the proposed RX provides a high RF gain and high out-of-band (OOB) blocker suppression to improve both the noise figure (NF) and OOB linearity. Particularly, our RX features enhanced filtering at the input side that can effectively prevent the OOB blockers from entering into the RX. By deriving its linear time-invariant (LTI) model, the input impedance matching, gain response and noise performance are analyzed. Besides that, a clock-delay technique is proposed to improve the LO non-overlap characteristics. Designed in 65-nm CMOS, the simulated results present that under an 80-MHz offset frequency, the RX scores a 29 dBm OOB-IIP3 and a −2.3 dBm B−1dB. The NF ranges between 3.2 to 6 dB, and the active area is 0.66 mm2. At 2 GHz, the power consumption is 25 mW, of which only 4.7 mW is due to the LO dynamic power |
Keyword | Bottom-plate Blocker-tolerant Gain-boosted (Gb) Linearity Low-noise Amplifier (Lna) Lo Generator N-path Filter Oob-iip3 Noise Figure (Nf) Switched-capacitor (Sc) |
DOI | 10.1109/OJCAS.2023.3335116 |
URL | View the original |
Indexed By | ESCI |
WOS Research Area | Engineering |
WOS Subject | Engineering, Electrical & Electronic |
WOS ID | WOS:001204990700004 |
Publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 |
Scopus ID | 2-s2.0-85193223640 |
Fulltext Access | |
Citation statistics | |
Document Type | Journal article |
Collection | Faculty of Science and Technology THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
Corresponding Author | Gengzhen Qi |
Affiliation | 1.School of Microelectronics Science and Technology, Sun Yat-sen University, Guangdong 510275, China 2.State-Key Laboratory of Analog and Mixed-Signal VLSI/IME, University of Macau, Macau, China |
Recommended Citation GB/T 7714 | Yi Mao,Gengzhen Qi,MAK PUI IN. Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique[J]. IEEE Open Journal of Circuits and Systems, 2014, 5, 92-101. |
APA | Yi Mao., Gengzhen Qi., & MAK PUI IN (2014). Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique. IEEE Open Journal of Circuits and Systems, 5, 92-101. |
MLA | Yi Mao,et al."Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique".IEEE Open Journal of Circuits and Systems 5(2014):92-101. |
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