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A 28-nm 18.7 TOPS/mm 2 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh
Zhan, Yi1; Yu, Wei Han1; Un, Ka Fai1; Martins, Rui P.1,2; Mak, Pui In1
2024-11
Source PublicationIEEE Journal of Solid-State Circuits
ISSN0018-9200
Volume59Issue:11Pages:3866-3876
Abstract

This article reports a high-density 3T1C single-finger (SF) embedded dynamic random access memory (eDRAM) compute-in-memory (CIM) macro. It features several techniques that enhance the memory density, the energy efficiency, and the throughput density, namely: 1) a high-density 3T1C SF-eDRAM cell with low-leakage retention (LLR) to improve the memory density significantly with a competitive retention time; 2) a bit-wise input-sparsity-aware (ISA) p-source input strategy for SF-eDRAM cell to save the energy dissipation of the eDRAM array; 3) a bit-significance-aware (BSA) analog-to-digital converter (ADC) to reduce the energy dissipation; and 4) a kernel-wise weight-update-and-refresh (KWUR) to improve the kernel-wise CIM utilization rate and the eDRAM-CIM macro throughput during weight update/refresh. The proposed 128-kb SF-eDRAM CIM macro prototyped in 28-nm CMOS exhibits a memory density of 2.28 Mb/mm $^2$ , reaches a peak throughput density of 18.7 TOPS/mm $^2$ , and a peak energy efficiency of 234.6 TOPS/W performing 8b operations.

KeywordCompute-in-memory (Cim) Deep Neural Network (Dnn) Embedded Dynamic Random Access Memory (Edram) Input-sparsity Single-finger (Sf) Weight Update/refresh
DOI10.1109/JSSC.2024.3387995
URLView the original
Indexed BySCIE
Language英語English
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:001324965400001
PublisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141
Scopus ID2-s2.0-85190776867
Fulltext Access
Citation statistics
Document TypeJournal article
CollectionTHE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU)
Faculty of Science and Technology
INSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding AuthorYu, Wei Han
Affiliation1.Department of Electrical and Computer Engineering, State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, Faculty of Science and Technology, University of Macau, Macau, China
2.Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisbon, Portugal.
First Author AffilicationFaculty of Science and Technology
Corresponding Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Zhan, Yi,Yu, Wei Han,Un, Ka Fai,et al. A 28-nm 18.7 TOPS/mm 2 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh[J]. IEEE Journal of Solid-State Circuits, 2024, 59(11), 3866-3876.
APA Zhan, Yi., Yu, Wei Han., Un, Ka Fai., Martins, Rui P.., & Mak, Pui In (2024). A 28-nm 18.7 TOPS/mm 2 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh. IEEE Journal of Solid-State Circuits, 59(11), 3866-3876.
MLA Zhan, Yi,et al."A 28-nm 18.7 TOPS/mm 2 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh".IEEE Journal of Solid-State Circuits 59.11(2024):3866-3876.
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