This article presents a 3 THz CMOS image sensor (Tera-CIS). The sensor has a column-parallel readout (CPRO) architecture that integrates an antenna-coupled pixel array and CPRO circuit chains on a monolithic chip. The proposed compact two-transistor (2T) pixel adopts a step-covered patch antenna and a defected ground structure (DGS) to obtain sufficient sensitivity and bandwidth. The step-covered patch antenna model is developed to predict pixel performances precisely. The DGS structure suppresses mutual coupling among adjacent pixels and shrinks the pixel pitch. In the CPRO circuit chain, chopping and oversampling techniques are employed to reduce noise and flexibly balance the dynamic range (DR) characteristics with the imaging rate. A digital decimation filter (DDF) with a time-multiplexing fashion is adopted to alleviate resource pressure. A 16.4k-pixel Tera-CIS was fabricated with a standard 0.18 $\mu $ m CMOS process. A 3 THz imaging platform with four different continuous-wave (CW) terahertz quantum cascade lasers was established. The pixel sensitivity was 753 V/W at 3.4 THz, with a measured detection bandwidth of 0.78 THz (from 3.08 to 3.86 THz). The DR in the voltage domain of the sensor reached 73 dB at 8 fps while the maximum DR in the power domain was 39.8 dB. Meanwhile, the sensor can operate up to 130 fps. The imaging system can achieve high-resolution imaging and clearly identify concealed objects.