| Residential College | false |
| Status | 已發表Published |
| A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM | |
Ren, Hongyu1; Yang, Zunsong1 ; Huang, Yunbo2; Feng, Chaoping1; Chen, Tianle1; Zhang, Xinming1; Meng, Xianghe1; Yan, Weiwei1; Zhang, Weidong1; Iizuka, Tetsuya3; Chen, Yong2 ; Mak, Pui In2; Han, Zhengsheng1; Li, Bo1
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| 2024-05 | |
| Source Publication | IEEE Microwave and Wireless Technology Letters
 |
| ISSN | 2771-957X |
| Volume | 34Issue:5Pages:548-551 |
| Abstract | A double-sampling phase-locked loop (DSPLL) with low jitter, low spur, and low power is presented. It uses low-ripple bootstrapped double-sampling phase detectors (DSPDs) to lower the PD’s in-band phase noise (PN) by about 4 dB without compromising the phase-locked loops (PLLs) spur level and power efficiency. A low-noise multimodulus divider (MMD) is proposed to avoid the use of power-hungry retimers after it, further improving the jitter-power figure of merit (FOM). With a 100-MHz input sinewave reference, the prototype in 28-nm CMOS achieves an rms jitter of 78 fs integrated from 1 k to 100 MHz, a spur level of $-$ 92 dBc with an FOM of $-$ 258 dB. The total power consumption is 2.6 mW at 6 GHz and the active area is 0.2 mm2. |
| Keyword | Double Sampling (Ds) Figure Of Merit (Fom) Frequency Synthesizer Low Jitter Low Spur Phase Detector (Pd) Phase-locked Loop (Pll) Phase Noise (Pn) Reference Sampling (Rs) Subsampling (Ss) Phase Locked Loops Type-i |
| DOI | 10.1109/LMWT.2024.3377117 |
| URL | View the original |
| Indexed By | SCIE |
| Language | 英語English |
| WOS Research Area | Engineering |
| WOS Subject | Engineering, Electrical & Electronic |
| WOS ID | WOS:001194063400001 |
| Publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 445 HOES LANE, PISCATAWAY, NJ 08855-4141 USA |
| Scopus ID | 2-s2.0-85189315252 |
| Fulltext Access | |
| Citation statistics | |
| Document Type | Journal article |
| Collection | Faculty of Science and Technology THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING |
| Corresponding Author | Yang, Zunsong; Han, Zhengsheng; Li, Bo |
| Affiliation | 1.Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China 2.Department of ECE, State-Key Laboratory of Analog and Mixed-Signal VLSI/Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China 3.School of Engineering, Systems Design Laboratory, The University of Tokyo, Tokyo, Japan |
| Recommended Citation GB/T 7714 | Ren, Hongyu,Yang, Zunsong,Huang, Yunbo,et al. A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM[J]. IEEE Microwave and Wireless Technology Letters, 2024, 34(5), 548-551. |
| APA | Ren, Hongyu., Yang, Zunsong., Huang, Yunbo., Feng, Chaoping., Chen, Tianle., Zhang, Xinming., Meng, Xianghe., Yan, Weiwei., Zhang, Weidong., Iizuka, Tetsuya., Chen, Yong., Mak, Pui In., Han, Zhengsheng., & Li, Bo (2024). A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM. IEEE Microwave and Wireless Technology Letters, 34(5), 548-551. |
| MLA | Ren, Hongyu,et al."A 6-GHz 78-fsRMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM".IEEE Microwave and Wireless Technology Letters 34.5(2024):548-551. |
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