Emerging high-speed wireless communications utilizing the mm-wave band put stringent jitter requirements on local oscillators (LOs), e.g., <97fs at 26GHz for 5G FR2 using 256-QAM, which demands a power-hungry PLL. To reduce the power consumption of the mobile terminal, the duty-cycled operation offered by 3GPP can be utilized. However, to support the ultra-reliable low-latency communication (URLLC), the receiver must frequently detect a possible scheduling grant occupying a short symbol width that can be down to 6.3μs for a mm-wave band using a high-frequency subcarrier of 120kHz. If a PLL can robustly lock within sub-μs, it can be turned off between scheduled receiving times for significant power and energy saving. One straightforward solution for generating low-jitter mm-wave LOs is combining sub-10GHz PLLs with frequency multipliers [1]. However, although equipped with harmonic-extraction techniques to reduce the cost of the frequency multiplier, the PLLs in [2] and [3] still need power- and area-hungry buffers for boosting the output power and suppressing the subharmonic spurs, limiting their FoMJ. Alternatively, the sub-sampling (SS) PLL [4] is a promising candidate for directly synthesizing an mm-wave LO since its inherent low in-band phase noise (PN) enables a wide bandwidth to suppress the VCO PN. Nevertheless, the SSPLL suffers from an inferior reference (ref.) spur and the effort to improve the isolation between the VCO and sub-sampling phase detector (SSPD) [5] impairs jitter, FoMJ, and area. Furthermore, fulfilling the switched-capacitor (SC) search and loop settling robustly within sub-μs is challenging for the SSPLL using an SSPD with a small capture range.