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7.4 A 0.027mm25.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrmsJitter and -74.2dBc Reference Spur
Huang, Yunbo2; Chen, Yong2; Yang, Zunsong1; Martins, Rui P.2,3; Mak, Pui In2
2024-03-13
Conference Name2024 IEEE International Solid-State Circuits Conference (ISSCC)
Source PublicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume67
Pages130-132
Conference Date18-22 February 2024
Conference PlaceSan Francisco
CountryUSA
PublisherIEEE
Abstract

A ring oscillator (RO) based phase-locked loop (PLL) is a promising candidate for multilane communication applications due to its small footprint, wide frequency tuning range, inherent multi-phase generation and frequency-pulling resilience. However, the RO suffers from inferior phase noise (PN) and a high flicker-noise corner, limiting the overall jitter performance. While the injection-locked clock multiplier (ILCM) [1] and the multiplying delay-locked loop (MDLL) [2] can effectively suppress the RO PN through the phase-realignment mechanism, the reference (REF) spur increases significantly due to the imperfect alignment timing, thus imposing a complex calibration. Type-I topology with a sampling phase detector or filter is attractive due to the inherent stability under high loop bandwidth (BW) [3], while the high phase detection gain (KPD) also helps to suppress the in-band noise. Still, the REF frequency limits the achievable phase margin (PM) bound of the sampling PLL, e.g., a maximum of 45° for a 1/4 fREF unit-gain BW [3], while increasing the REF frequency increases the crystal oscillator cost. Although the insertion of the REF frequency multiplier before the main PLL can relieve the BW-stability tradeoff, the digital background calibration typically requires an excessively long settling time eventually reaching milliseconds [4]. Alternatively, cascading the closed-loop sampling delay-locked loop [5] or the open-loop feedforward PN cancellation block [6] after the main PLL can lead to a large PN filtering effect. Yet, the additional high-frequency voltage-controlled delay line results high power consumption and the open-loop feedforward PN cancellation scheme requires off-chip gain calibration.

DOI10.1109/ISSCC49657.2024.10454291
URLView the original
Language英語English
Scopus ID2-s2.0-85188103612
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Citation statistics
Document TypeConference paper
CollectionFaculty of Science and Technology
INSTITUTE OF MICROELECTRONICS
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation1.Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China
2.University of Macau, Macao
3.Instituto Superior Tecnico, University of Lisboa, Lisbon, Portugal
First Author AffilicationUniversity of Macau
Recommended Citation
GB/T 7714
Huang, Yunbo,Chen, Yong,Yang, Zunsong,et al. 7.4 A 0.027mm25.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrmsJitter and -74.2dBc Reference Spur[C]:IEEE, 2024, 130-132.
APA Huang, Yunbo., Chen, Yong., Yang, Zunsong., Martins, Rui P.., & Mak, Pui In (2024). 7.4 A 0.027mm25.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrmsJitter and -74.2dBc Reference Spur. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 67, 130-132.
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