Two circuit techniques for performance enhancement of high-speed flash ADCs are proposed. A calibration-intensive dynamic comparator features an improved built-in reference voltage generation scheme to alleviate the issue of kickback noise, and a proper reset function to clean the memory effect due to the dielectric relaxation in the capacitors, yielding better static and dynamic linearity performances. The second is a split-ROM encoder, which halves the signaling path to lower the parasitics, while boosting the back-end processing speed with small power. The feasibility of them is demonstrated via a 5-bit flash ADC designed in 65nm CMOS. With 3.69mW of power, the ADC operated at 2GS/s exhibits an ENOB of >4.5 bits up to an ERBW of 3.6GHz. The DNL and INL are within +0.091/-0.071 and +0.066/-0.062 LSB, respectively.