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A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS
Lu, Xin1; Wu, Jiangchao1; Wang, Zhao1; Xiang, Yifei1; Liu, Liyuan2; Mak, Pui In1; Martins, Rui P.3; Law, Man Kay1
2024
Source PublicationIEEE Transactions on Circuits and Systems II: Express Briefs
ISSN1549-7747
Volume71Issue:8Pages:3635 - 3639
Abstract

This paper presents a compact gated ring oscillator (GRO) based cyclic time-to-digital converter (TDC) for single-photon emission computed tomography, 3D cameras, and fluorescence lifetime imaging microscopy. With a single GRO serving as both the quantizer and residue generator, the GRO period can serve as the time reference to achieve intrinsic coarse-fine conversion. The proposed cyclic TDC also features a phase domain reset scheme which generates a compensation pulse for purging the GRO phase residue among consecutive conversion cycles. Fabricated in 65nm CMOS, this work occupied an area of 0.013mm2. The proposed TDC achieves a high resolution of 3.1ps together with an extended input range of 3.2ns. Consuming 1.41mW at 36MS/s from a 1-V supply, it also demonstrates a measured DNL and INL of +0.5/-0.6LSB and +3.3/-3.6LSB, respectively.

KeywordCoarse-fine Conversion Cyclic Time-to-digital Converter (Tdc) Delays Gated-ring Oscillator (Gro) Generators Image Edge Detection Logic Gates Phase Domain Reset Ring Oscillators Signal Resolution Switches
DOI10.1109/TCSII.2024.3367177
URLView the original
Indexed BySCIE
Language英語English
WOS Research AreaEngineering
WOS SubjectEngineering, Electrical & Electronic
WOS IDWOS:001283904700059
PublisherInstitute of Electrical and Electronics Engineers Inc.
Scopus ID2-s2.0-85186096839
Fulltext Access
Citation statistics
Document TypeJournal article
CollectionDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
INSTITUTE OF MICROELECTRONICS
Corresponding AuthorLaw, Man Kay
Affiliation1.AMSV, Institute of Microelectronics and FST-ECE, University of Macau, Macau, China
2.Institute of Semiconductors, State Key Laboratory of Superlattices and Microstructures, Chinese Academy of Sciences, Beijing, China
3.Institute of Microelectronics and FST-ECE, AMSV, University of Macau, China
First Author AffilicationFaculty of Science and Technology
Corresponding Author AffilicationFaculty of Science and Technology
Recommended Citation
GB/T 7714
Lu, Xin,Wu, Jiangchao,Wang, Zhao,et al. A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(8), 3635 - 3639.
APA Lu, Xin., Wu, Jiangchao., Wang, Zhao., Xiang, Yifei., Liu, Liyuan., Mak, Pui In., Martins, Rui P.., & Law, Man Kay (2024). A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS. IEEE Transactions on Circuits and Systems II: Express Briefs, 71(8), 3635 - 3639.
MLA Lu, Xin,et al."A 0.013mm2 3.2ns Input Range 10-bit Cyclic Time-to-Digital Converter Using Gated Ring Oscillator With Phase Domain Reset in 65nm CMOS".IEEE Transactions on Circuits and Systems II: Express Briefs 71.8(2024):3635 - 3639.
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