The fsRMS jitter fractional-N (FN) phase-locked loop (PLL) is essential for high-speed wireless/wireline transceivers and data converters. Several reported low-jitter FN-PLLs are listed in Fig. 1. Both the sampling phase detector (SPD) [1] and the bang-bang PD (BBPD) [2] based PLLs assisted by the digital-To-Time converter (DTC) leverage high phase-detection gain (KPD) to suppress the in-band phase noise (PN). Regrettably, the low-jitter DTC with sufficient tuning range and linearity is required to avoid jitter degradation at the cost of power and figure-of-merit (FoM) improvement. To prevent the DTC-induced issue, the voltage-domain digital-To-Analog (VDAC) based sub-sampling PLL (SS-PLL) replaces a DTC with a VDAC, whose noise can be suppressed by high KPD [3]. Yet, the usage of the digitally-controlled delay line (DCDL) to keep high KPD adds extra noise. Particularly, the noises of the DTC and DCDL vary much with process, voltage, and temperature (PVT) variation, thus sensitizing the PLL jitter over PVT variation; and both DTC and VDAC necessitate complicated calibration to cope with their gain mismatch or nonlinearity, thus occupying large area. Alternatively, widely used charge-pump-based PLL (CP-PLL) [5], [6] is robust and free of DTC or VDAC, and the CP nonlinearity is addressed by the offset CP (OCP) [5], whereas the long turn-on time (ton) of the OCP and low KPD elevate the in-band PN, and the integral capacitor is bulky.