Conventional ADCs require a low-noise power supply from the power delivery network (PDN). The commonly used PDN consists of a DC-DC converter that boosts or bucks the external power source to the desired voltage level and a low dropout (LDO) regulator is required to suppress the ripple from DC-DC. However, the power efficiency of this type of PDN is limited by the dropout voltage of the LDO. Moreover, the DC-DC itself needs to provide a higher voltage output to counteract this dropout voltage and the higher conversion ratio results in a lower efficiency. Therefore, to enhance the power efficiency, this work proposes a 10MHz BW 2-channel time-interleaved noise-shaping SAR ADC (TI-NS-SAR) directly powered by an on-chip boost DC-DC converter for both supply VDD and reference VREF, without using LDO. As the VREF is the most sensitive node of the NS-SAR, the DC-DC's ripple is directly injected into the ADC through VREF causing the performance drop. Some existing techniques can suppress the ripple originated inside the ADCs; like decoupling capacitors, ripple cancellation/calibration techniques in [1,2], etc. However, they still need a low-noise external VREF. They are not the corresponding solutions to the ripple originating from the external PDN. Therefore, to mitigate the interference to the ADC from the ripple generated by the on-chip DC-DC, this work utilizes proper frequency management and ripple noise shaping technique, based on the co-design of the NS-SAR and the DC-DC.