Energy-efficient low-noise comparator is imperative for successive approximation register (SAR) analog-to-digital converters (ADC) deployed in cutting-edge applications, such as wireless sensing and biomedical implants. Incorporating a preamplifier with high gain in the comparator induces a substantial voltage swing at the preamplifier's output, thereby reducing noise levels. Nonetheless, previous works including the strong-arm comparator [1], Elzakker comparator [2], and dynamic bias comparator [3][4] all suffered from poor FoM₁ = (Energy × Noise Power) due to the small gain (>10) of the preamplifier. To augment the preamplifier s gain without sacrificing FoM₁, the dynamic floating inverter amplifier (FIA) comparator [5] adopted a straightforward approach, utilizing complementary input transistors with 2 times current reuse as shown in Fig. 1. This work attained a moderate gain of approximately 30, resulting in an improved FoM₁ of 2.07nJμV². The preamplifier s gain is improved by 2 times theoretically compared with [5] by stacking two inverters with 4 times current reuse [6]. Despite the improved FoM₁ of 0.69nJμV², the additional reservoir capacitor C_S2 due to the stacked inverter incurs an area penalty, and the bias generation circuits connected to the comparator input can also result in extra input noise. In this work, we proposed a FIA-based comparator with 4 times current reuse without any extra reservoir capacitor and bias generation circuits. Furthermore, the incorporation of cross-coupled inverters within the input transistor pairs elevates the preamplifier s gain to 224 while maintaining an input referred noise of 27.3μV at an energy consumption of 0.25pJ per comparison. Consequently, this work can achieve a state-of-the-art FoM₁ of 0.19nJμV².