Latest wireless communication systems desire ADCs to pursue wide-BW (160MHz) and high-DR (65dB) to support ever-increasing data transfer rates and higher-order modulation schemes. Continuous-time (CT) pipeline ADC/DSM draws growing attention as it combines the easy-to-drive and inherent anti-aliasing merits of CT operation with adequate resolution from pipeline operation, where OSR is restricted by high sampling frequency (Fs). Meanwhile, when GHz-Fs is utilized to broaden the signal BW in the CT pipeline converter, two design issues arise related to the front-end stage: 1) path delay mismatch between input signal path and quantization (QTZ) path; 2) image signal produced by switching of DAC on QTZ path, which lies on integer multiples of Fs and easily saturates the backend stage. This paper proposes a CT pipeline DSM with correlative passive RC low-pass filters (LPFs) that help alleviate the abovementioned issues. The DAC image filtering in residue amplifier (RA) is moved to the QTZ path and realized by a simple RC-LPF2, which pre-filters the DAC image before the DAC current is injected into the RA, reducing the RA's swing, slew rate, and its associated power consumption. On the other hand, another RC-LPF1 is inserted into the analog signal path to emulate the required delay that matches the operation time of the QTZ path. Benefits from the RC components correlation between RC-LPF1 and RC-LPF2, this structure avoids the usage of the LC- or tuned-RC-lattice all-pass/low-pass filter (APF/LPF) in the front-end stage [1-3]. For the back-end design, an APF analog delay is proposed to be inserted in the CIFF CTDSM to restore the STF=1 under the ELD effect, maintaining matching simplicity between analog and digital domains.