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| Status | 已發表Published |
| A Multi-Phase Multi-Path Hybrid Buck Converter for 9-48V to 0.8-1.2V Conversion with Improved DCR-Loss Reduction and Alleviated CFLY Current Gathering Achieving 88.3% Peak Efficiency and 176A/cm3Density | |
Qiaobo Ma1,2 ; Huihua Li1,2; Jiahao Shi1,2; Yang Jiang1,2  ; Rui Martins1,2,3; Pui-In Mak1,2
| |
| 2024-05 | |
| Conference Name | 2024 IEEE Custom Integrated Circuits Conference (CICC) |
| Conference Date | 21-24 April 2024 |
| Conference Place | Denver, CO, USA |
| Publisher | IEEE |
| Abstract | With the surging demand for automotive electronics and USB PD standard devices, 48V architecture point-of-load (PoL) DC-DC converters play an essential role in optimizing system performance and minimizing energy consumption. However, it is challenging to simultaneously achieve enhanced output current capability, high efficiency and power density under high input voltage, especially with high step-down ratios. To address these issues, dual-path (DP) switched-capacitor-inductor (SCI) hybrid converters were introduced [1]–[2], aiming to reduce conduction loss in the inductor DC resistance (DCR), enabling reduced inductor size and improved power density. Alternatively, a DP structure combining a switched-capacitor (SC) stage alleviates high input voltage induced losses by reducing high-voltage (HV) switch current. However, these topologies face voltage conversion ratios (VCR) limitations for 48V high-step-down PoL systems, leading to conduction loss and output voltage ripple issues induced by the flying-capacitor (CF) current(I CF ) gathering effect when the duty ratio (D) approaches an extreme level. This work introduces a multi-phase multi-path hybrid (M2H) buck converter for high-step-down conversions with enhanced inductor current (lL,DC) reduction and alleviated lCF gathering. In addition, it features a switch conduction characteristic that ensures high-voltage (HV) switches pass lower current while low-voltage (LV) switches conduct higher current, maximizing the advantage of LV switches and thereby improving efficiency and on-chip power density. An operation-mode control method and gate driver scheme are also proposed to ensure reliable switch control across a wide VCR range. For a 9-48V to 0.8-1.2V conversion, the proposed converter achieves a measured peak efficiency of 88.3% and a current density of 176A/cm 3 using power components with a total volume of 11.35mm 3 . |
| DOI | 10.1109/CICC60959.2024.10528992 |
| URL | View the original |
| Fulltext Access | |
| Citation statistics | |
| Document Type | Conference paper |
| Collection | INSTITUTE OF MICROELECTRONICS |
| Corresponding Author | Yang Jiang |
| Affiliation | 1.State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macao 2.ECE Department, Faculty of Science and Technology, University of Macau, Macao 3.On leave from Instituto Superior Tecnico, Universidade de Lisboa, Lisboa, Portugal |
| First Author Affilication | University of Macau; Faculty of Science and Technology |
| Corresponding Author Affilication | University of Macau; Faculty of Science and Technology |
| Recommended Citation GB/T 7714 | Qiaobo Ma,Huihua Li,Jiahao Shi,et al. A Multi-Phase Multi-Path Hybrid Buck Converter for 9-48V to 0.8-1.2V Conversion with Improved DCR-Loss Reduction and Alleviated CFLY Current Gathering Achieving 88.3% Peak Efficiency and 176A/cm3Density[C]:IEEE, 2024. |
| APA | Qiaobo Ma., Huihua Li., Jiahao Shi., Yang Jiang., Rui Martins., & Pui-In Mak (2024). A Multi-Phase Multi-Path Hybrid Buck Converter for 9-48V to 0.8-1.2V Conversion with Improved DCR-Loss Reduction and Alleviated CFLY Current Gathering Achieving 88.3% Peak Efficiency and 176A/cm3Density. . |
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