This article presents a 12-GS/s 12-bit 4× time-interleaved (TI) pipelined analog-to-digital converter (ADC), which utilizes a global dither injection (GDI) scheme to facilitate an input-independent background timing skew calibration. The GDI scheme adds dithers into the input signal of the push-pull source follower (PP-SF) in the input buffer (IBF), avoiding undetectable skews in conventional local dither injection (LDI) schemes. Meanwhile, the perturbations between the input signal and dither are mitigated by cross-coupled capacitive networks. This work also significantly improves the efficiency of the interleaver using the following techniques: first, the PP-SF-based IBF is linearized by a self-adaptive current compensation (SACC), achieving high linearity under 1.2-V low supply voltage headroom. Second, the speed of the 12-bit channel is lifted to 3 GS/s in 28-nm CMOS using a sturdy ring amplifier (SRingAmp) with feedforward (FF), which enables a nonhierarchical interleaver with a small interleaving factor of 4×. The time-interleaved ADC attains a 54.1-dB SNDR and a 66.0-dB SFDR under a near-Nyquist input with 179.8-mW power consumption, translating into a Walden figure of merit (FoM) of 36.2 fJ/conversion step and a Schreier FoM of 159.3 dB.