This paper proposes a sub-nW PMOS-only voltage reference (VR) for low-power application. The proposed VR uses a 2-transitor (2-T) pre-regulation (PR) circuit to supply a 2-T core circuit for reducing the dependence of the reference voltage (VREF) on the supply voltage (VDD). Both the core and the PR circuit are biased by the leakage current of the PMOS transistors. Gate and bulk feedback are utilized in the PR circuit to further improve the line sensitivity (LS) and the power supply rejection ratio (PSRR) without any other extra transistors. The proposed 0.18-μJm CMOS process, while 7 samples have been measured. The design can generate a VREF of 235.6 mV and consume a supply current of 0.31 nA under a minimum VDD of 0.45 V at 25° C. The PSRRs measured at frequencies of 100 Hz and 1 kHz are -77 dB and -72 dB respectively. Moreover, the average LS is 0.033 %/V when the VDD varies from 0.45 V to 1.8 V. The average temperature coefficient (TC) is 66.3 ppm/°C without trimming over the temperature range of -40°C to 85°C. The minimum power consumption is 140 pW, and the chip area is only 0.0007 mm2.