Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction

doi:10.1109/TCSII.2025.3526921

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	Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction
	Xu, Tailong 1,2; Li, Haoran 3; Meng, Xi 3,4; Zhan, Xiangxun 3; Peng, Yatao 3; Yin, Jun3 ; Yang, Shiheng 5; Fan, Chao 6; Huang, Zhixiang 7; Martins, Rui P.8,9 ; Mak, Pui In3
	2025
Source Publication	IEEE Transactions on Circuits and Systems II: Express Briefs
ISSN	1549-7747
Abstract	This paper analyzes the phase noise (PN) and reference (REF) spur performance of the reference-sampling (RS) PLL when the total sampling capacitor (CS) is reduced to save the power consumption of the crystal oscillator (XO) buffer. Based on the analysis, the saved power consumption from the XO buffer can be utilized to improve the PN of the voltage-controlled oscillator (VCO), which compensates for the in-band PN degradation induced by the CS reduction. Based on this theme, we can reduce the total power consumption of the RS-PLL and the XO buffer without degrading the output root-mean-square (RMS) jitter by reducing CS if a VCO with a high figure-of-merit (FoM) and a low 1/f PN corner frequency is available. A type-II RS-PLL prototype utilizing a gain-boosting RS phase detector to suppress the voltage-to-current (G) circuit noise is designed to verify the presented design strategy. With the aid of an inverse-class-F VCO with a FoM of 190.4 dBc/Hz at 1 MHz offset frequency and a 1/f PN corner frequency of 300 kHz across the frequency tuning range from 5.2 GHz to 6.1 GHz, the RS-PLL prototype fabricated in a 65-nm CMOS achieves low RMS jitter and REF spur of 64.8 fs and -84.1 dBc, respectively, while dissipating 6.9 mW, corresponding to a jitter-power FoM (FoM) of -255.4 dB.
Keyword	Gain-boosting phase detector jitter phase noise phase-locked loop reference spur reference-sampling
DOI	10.1109/TCSII.2025.3526921
URL	View the original
Language	英語English
Scopus ID	2-s2.0-85214673740
Fulltext Access	View Full-Text via DOI View Full-Text via Scopus
Citation statistics
Document Type	Journal article
Collection	INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Affiliation	1.Hefei University, School of Advanced Manufacturing Engineering, Department of Electronic Information Engineering, Hefei, Anhui, 230601, China 2.University of Macau, Faculty of Science and Technology (FST), State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics (IME), The Department of Electrical and Computer Engineering (ECE), Macao, 999078, Macao 3.University of Macau, State Key Laboratory of Analog and Mixed-Signal VLSI, IME, ECE-FST, Macao, 999078, Macao 4.Marvell Asia Pte, Ltd, 369522, Singapore 5.University of Electronic Science and Technology of China (UESTC), School of Integrated Circuit Science and Engineering, Chengdu, Sichuan, 610054, China 6.Xi'an Jiaotong University, School of Microelectronics, Xi'an, Shannxi, 710049, China 7.Anhui University, Key Laboratory of Electromagnetic Environmental Sensing of Anhui Higher Education Institutes, Hefei, Anhui, 230601, China 8.University of Macau, State-Key Laboratory of Analog and Mixed-Signal VLSI, IME, ECE-FST, Taipa, Macao 9.Universidade de Lisboa, Instituto Superior Técnico, Lisboa, 1649-004, Portugal
First Author Affilication	Faculty of Science and Technology
Recommended Citation GB/T 7714	Xu, Tailong,Li, Haoran,Meng, Xi,et al. Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2025.
APA	Xu, Tailong., Li, Haoran., Meng, Xi., Zhan, Xiangxun., Peng, Yatao., Yin, Jun., Yang, Shiheng., Fan, Chao., Huang, Zhixiang., Martins, Rui P.., & Mak, Pui In (2025). Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction. IEEE Transactions on Circuits and Systems II: Express Briefs.
MLA	Xu, Tailong,et al."Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction".IEEE Transactions on Circuits and Systems II: Express Briefs (2025).

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