This brief presents a low-power compression-based CMOS image sensor for wireless vision applications. The sensor implements low-bit-depth imaging with planned sensor distortion (PSD) to effectively compress both data bandwidth and processing power while maintaining high reconstruction image quality. Accordingly, a column-parallel microshift-guided successive-approximation-register (SAR) ADC is proposed to enable 3-bit PSD imaging based on a 3× 3 pattern. To support normal imaging with low area overhead, the circuit is reconfigurable as an 8-bit SAR/single-slope ADC. The data bandwidth is further compressed by a customized lossless encoder based on predictive coding and run length coding. A 256× 216 prototype imaging system composed of the compression-based image sensor and the lossless encoder is fabricated in a 0.18-μ m standard CMOS process. Measurement results show that the image sensor achieves 3 bit/pixel (bpp) with 34.9-dB reconstruction peak signal-to-noise ratio (PSNR) and 0.91 structural similarity index (SSIM). With 1/4 spatial downsampling and lossless encoding, 0.31 bpp is obtained with 29.2-dB PSNR and 0.83 SSIM. The sensor consumes 14.8 μ W (full resolution) and 4.3 μ W (downsampling) at 15 fps, achieving state-of-the-art FoMs of 17.8 and 5.2 pJ/pixel frame, respectively. Including the encoder, the overall system dissipates as low as 1.2 μ J making it an attractive solution for wireless sensor networks.