Analog-to-information converters (AICs) take advantage of the limited information bandwidth in high-frequency signals to improve the energy efficiency of front-end data converters. High-resolution image sensors often convey limited information due to the spatial redundancy between neighboring pixels. This paper proposes a mixed-signal AIC which compresses each nonoverlapping 4 × 4 pixel block in a 816 × 640 pixel prototype active-pixel sensor (APS) imager. It combines an energy-efficient charge-pump bit-image processor (BIP) with an area-efficient successive-approximation-register-single-slope (SAR-SS) hybrid analog-to-digital converter (ADC) via a charge-transfer- amplifier (CTA). The AIC is fully dynamic and consumes no static power. The ADC's capacitor array doubles as a computational device for parts of the compression algorithm which reduces its sampling rate by a factor of four. The compressed data contains direct edge information and can be decoded by a very simple receiver. The fabricated prototype consumes 12 pJ per pixel at 111 fps in the image compression mode and 48 pJ per pixel at 28.7 fps in raw data mode (9 b per pixel) under the same clock rate. To the best of our knowledge, this is the most energy-efficient compressive CMOS image sensor ever reported in the literature, thanks to the proposed AIC. © 1966-2012 IEEE.