A local silicon-gate carbon nanotube field effect transistor (CNFET) configuration has been proposed and implemented for integration purpose. By combining the advantages of in situ carbon nanotube growth technology and the silicon-on-insulator technology, we have realized the CNFETs with individual device operation, low parasitic capacitance, high yield fabrication, and better compatibility to the complementary-metal-oxide-semiconductor (CMOS) process. The CNFETs show up-to-date electrical performance. The scaling effect of gate oxide is also explored. This configuration makes CNFET a step closer to the CMOS integrated circuit application. © 2006 American Institute of Physics.