This article reports a 4th-order 100-MHz bandwidth continuous-time (CT) delta-sigma modulator in 28-nm CMOS. A preliminary sampling and quantization (PSQ) technique is presented, which allows almost a full utilization of the clock period for the quantization to extend the available conversion time of the backend quantizer (QTZ) under a 0.65 excess loop delay (ELD) coefficient. With the PSQ, both the sampling and quantization of the backend QTZ are splitted into two steps, coarse and fine, similar to the subranging architecture to save power. The QTZ runs at 2 GHz achieving 7 bit (1 b error correction) with only 1.4-mW power. By adding a feedforward ELD compensation path in the cascade of integrators of the cascade of integrators in feedforward (CIFF) topology, only one digital-to-analog converter (DAC) is necessary in this design. The modulator attains a signal bandwidth of 100 MHz with 72.6-dB signal-to-noise and distortion ratio (SNDR) while only consuming 16.3 mW from 1.1- and 1.5-V power supplies. The prototype has a dynamic range of 76.3 dB and a Schreier FoM of 174.2 dB with an active area of 0.019 mm2.