A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler

doi:10.1109/TCSI.2020.3039252

UM > THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU)

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	A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler
	Jiang,Wenning1 ; Zhu,Yan1 ; Chan,Chi Hang1 ; Murmann,Boris 2; Martins,Rui Paulo1
	2020-12-08
Source Publication	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
ISSN	1549-8328
Volume	68 Issue:2 Pages:557-568
Abstract	This paper presents a two-way time-interleaved (TI) 7-bit 2-GS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The design achieves wideband operation with an effective resolution bandwidth (ERBW) in the 3rd Nyquist zone. The converter's front-end employs current integrating (CI) sampler that provide both buffering and anti-alias (AA) filtering at low power dissipation. Facilitated by the CI-samplers' inherent inter-sample interactions, the timing mismatch among the TI channels can be detected in the amplitude domain, obviating the need for a dedicated reference channel for background calibration. After calibration, the ADC achieves 36.4 dB signal-to-noise-and-distortion ratio (SNDR) near Nyquist and >2.6 GHz ERBW at a sampling rate of 2 GS/s. The ADC's power consumption is 7.62 mW (including the CI buffer) and its Walden figure of merit (FoMw) is 70.8 fJ/conversion-step.
Keyword	Analog-to-digital Converter Sar Adc Time-interleaved Adc Current Integrating Sampler Background Timing Skew Calibration Timing Skew
DOI	10.1109/TCSI.2020.3039252
URL	View the original
Indexed By	SCIE
Language	英語English
WOS Research Area	Engineering
WOS Subject	Engineering, Electrical & Electronic
WOS ID	WOS:000608691300001
Scopus ID	2-s2.0-85097939842
Fulltext Access	View Full-Text via DOI View Full-Text via Web of Science View Full-Text via Scopus
Citation statistics
Document Type	Journal article
Collection	THE STATE KEY LABORATORY OF ANALOG AND MIXED-SIGNAL VLSI (UNIVERSITY OF MACAU) INSTITUTE OF MICROELECTRONICS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
Corresponding Author	Chan,Chi Hang
Affiliation	1.State Key Laboratory of Analog and Mixed Signal VLSI,Institute of Microelectronics,University of Macau,Macao 2.Department of Electrical Engineering,Stanford University,Stanford,United States
First Author Affilication	University of Macau
Corresponding Author Affilication	University of Macau
Recommended Citation GB/T 7714	Jiang,Wenning,Zhu,Yan,Chan,Chi Hang,et al. A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 68(2), 557-568.
APA	Jiang,Wenning., Zhu,Yan., Chan,Chi Hang., Murmann,Boris., & Martins,Rui Paulo (2020). A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 68(2), 557-568.
MLA	Jiang,Wenning,et al."A 7-bit 2 GS/s Time-Interleaved SAR ADC with Timing Skew Calibration Based on Current Integrating Sampler".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 68.2(2020):557-568.

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